1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a sense amplifier.
2. Background of Related Art
A main amplifier generally uses a voltage sensing method or a current sensing one. The voltage sensing method will now be described.
A signal, amplified by a sense amplifier, is transmitted from a bit line to a data sense amplifier by column selection. Since the sense amplifier is connected in common in a single cell array block, a long wiring length is needed, which makes it difficult to transmit signals at high speed. There is a need to develop a high-sensitivity data sense amplifier that reduces the parasitic capacitance and resistance through such wiring.
FIG. 1 is a circuit diagram of a related art main amplifier using a voltage sensing method. As shown in FIG. 1, a main amplifier using the voltage sensing method includes a first-stage amplifying part 11, a first enabling part 13 that drives the first-stage amplifying part 11, a second-stage amplifying part 15 and a second enabling part 17 that drives second-stage amplifying part 15.
The first-stage amplifying part 11 has first and second differential amplifiers 11a and 11b, and the second amplifying part 15 has third and fourth differential amplifiers 15a and 15b. The first and second enabling parts 13 and 17 each are a metal oxide semiconductor (MOS) transistor. In the related art main amplifier using the voltage sensing method, the first-stage amplifying part 11 is driven by the first enabling part 13 to amplify an applied signal. The amplified signal is transmitted to second-stage amplifying part 15 to be amplified a second time. The differential amplifier is also called a data bus sense amplifier, and consists of a current mirror with four transistors.
Transistors Q1, Q2, Q3 and Q4 constitute the first differential amplifier 11a, and transistors Q5, Q6, Q7 and Q8 form the second differential amplifier 11b. Transistors Q9, Q10, Q11, and Q12 and transistors Q13, Q14, Q15, and Q16 respectively constitute the third differential amplifier 15a and the fourth differential amplifier 15b. One of a data bus DB and a data bus DB, which are precharged "high" during a data read, transitions "low" from output data of a bit-line sense amplifier (not shown), and the other one maintains a "high" level. A low-level signal is applied to an input terminal of the transistor Q1, and a high-level signal is input to an input terminal of the transistor Q2. A low-level signal is applied to an input terminal of the transistor Q5, and a high-level signal is input to the transistor Q6. If a driving signal is input to first enabling part 13, the MOS transistor is turned on. The signal, amplified once by the first differential amplifier 11a, is transmitted to the third and fourth differential amplifiers 15a and 15b of the second-stage amplifying part 15. Similarly, the signal, amplified once by the second differential amplifier 11b, is sent to the third and fourth differential amplifiers 15a and 15b of the second-stage amplifying part 15.
As shown in FIG. 1, the signal, amplified by the first differential amplifier 11a, is simultaneously applied to a gate of the transistor Q9 of the second-stage amplifying part 15 and a gate of the transistor Q13. The signal, amplified by the second differential amplifier 11b, is concurrently applied to a gate of the transistors Q10 and Q14 of the second-stage amplifying part 15. The third and fourth differential amplifiers 15a and 15b amplify the first amplified signal and produce the same through an output buffer (not shown).
FIG. 2 is a circuit diagram of a related art main amplifier using the current sensing method. The related art main amplifier using the current sensing method includes a current/voltage converter 21 and a differential amplifying part 23 amplifying a signal converted into a voltage.
The current/voltage converter 21 converts a current into a voltage and is constituted by a current mirror having four transistors M1, M2, M3 and M4. A signal, output from a bit-line amplifier (not shown), is input to a source of the transistor M2 and a drain of the transistor M4. Biases 1, 2 and 3 are applied to the transistors M1, M2 and M3 so that each transistor is actuated in the saturation region.
In the related art current amplifier using the current sensing method, the applied current signal is applied not to the gate of one of the transistors M1, M2 and M3 but to the transistor M4 actuated in the linear region. Therefore, the voltage equivalent to the current is produced from a gate of the transistor M4. The voltage, output from the gate of the transistor M4, is transmitted to differential amplifying part 23 and then amplified, before being output through the output buffer (not shown).
FIG. 3 graphically shows the result of simulation of the related art main amplifier of the voltage sensing method. As shown in FIG. 3, as an input signal and an enabling signal are applied to the main amplifier, the main amplifier is enabled to amplify the signal. It takes about 2.7 nanoseconds (ns) until the main amplifier produces an output signal.
As described above, the related art main amplifiers have various problems. In the main amplifier using the voltage sensing method, the signal produced from the bit-line amplifier (the input signal of the main amplifier) is applied to each gate of the transistors of the differential amplifying parts, which causes a transmission delay. The transmission delay is a severe problem for a highly-integrated semiconductor device because of the large parasitic capacitance. The amplification speed of the related art main amplifier of voltage sensing method is lower than that of current sensing method. In the related art current main amplifier, since biases 1, 2 and 3 are applied so that each transistor is actuated in the saturation region, the main amplifier of the current sensing method varies with a power supply voltage level. When the power supply voltage is low and a transmission line is long, significant time can be required to convert the current into a voltage. Such delay can be a problem for a highly-integrated semiconductor device.